FIG. 1 shows two key components of an electronic module. A chip 100 is made of silicon on which electronic circuits are fabricated. A substrate 102 is made of organic materials embedded with copper interconnects. A substrate 102 facilitates electrical interconnection of the chip to external electronic circuits on a motherboard.
The density of connection points (controlled collapse chip connection, or “C4s”) between a chip 100 and a substrate 102 is a critical parameter. A larger number of C4s requires multiple build-up layers 104 to achieve the needed electrical connections to the motherboard. A typical substrate 102 may have four build-up layers 104 on top and bottom and support about 3,000 C4s. FIG. 1 shows stacked vias 106 as well as staggered vias 108 needed to complete the interconnection. Stacked vias 106 are often preferable because they achieve a C4 connection density upwards of 20% as compared to a staggered via 108.
FIG. 2 shows the known art with regard to a stacked via 206 and a plated through hole 210 (PTH). An individual stacked via 206 as shown in FIG. 2 accumulates various levels of strain as it is thermally cycled. In a planar view the stacked vias 206 are located wherever it is convenient to embed them by the electrical designer of a substrate. The coefficient of thermal expansion (CTE) of various materials used to construct a module is not matched and is known to drive thermomechanical stresses within a module. Repeated thermal cycling of an electronic module exhibits failure at via interface regions due to thermomechanically driven accumulated strain. An individual via stack 206 is strained along the Z-axis as well as the (X-Y) plane by the CTE-driven thermo-mechanical stresses.